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information in this document is provided solely to enable use of intel products. intel assumes no liability whatsoever, includi ng infringement of any patent o r copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. inf ormation contained herein supersedes previously published specifications on these devices from intel . ? intel corporation 1995 january 1999 order number: 243667-003 intel a pentium a ii processor mobile module: mobile module connector 1 (mmc-1) n intel mobile pentium ii processor with core frequency running at speeds of 300 mhz, 266 mhz, and 233 mhz n processor core voltage regulation supports input voltages from 5v to 21v ? above 80 percent peak efficiency n integrated active thermal feedback (atf) system ? acpi rev. 1.0 compliant ? internal a/d C digital signaling (smbus) across the module interface ? programmable trip point interrupt or poll mode for temperature reading n thermal transfer plate for heat dissipation n intel 443bx host bridge system controller ? dram controller supports edo and sdram at 3.3v ? supports pci clkrun# protocol ? sdram clock enable support and self refresh of edo or sdram during suspend mode ? 3.3v pci bus control, rev 2.1 compliant the intel a pentium a ii processor mobile module connector 1 (mmc-1) is a highly integrated assembly containing an intel pentium ii mobile processor and its immediate system-level support. the module interfaces electric ally to its host system via a 3.3-v pci bus, a 3.3-v memory bus and intel 443bx host bridge control signals.
2 intel a pentium a ii processor mobile module mmc-1 information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life-saving, or life-sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium a ii processor mobile modules may contain design defects or errors known as errata. current characterized errata are available o n request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtain ed by calling 1-800- 548-4725 or by visiting intels website at http://www.intel.com copyright ? intel corporation1998. *third-party brands and names are the property of their respective owners.
3 intel a pentium a ii processor mobile module mmc-1 contents 1.0 introduction ..................................................5 1.1 revision history ....................................................5 2.0. architecture overview ............................5 3.0 module connector interface................7 3.1 signal definition....................................................7 3.1.1. signal list..............................................................8 3.1.2. memory (108 signals) ..........................................9 3.1.3. pci (56 signals)..................................................10 3.1.4 processor and piix4e sideband (9 signals).....11 3.1.5 power management (8 signals).........................12 3.1.6 clock (8 signals).................................................13 3.1.7 voltages (39 signals) .........................................14 3.1.8 jtag (7 signals) ................................................14 3.1.9 miscellaneous (45 signals) ................................15 3.2. connector pin assignments ...............................16 3.3 pin and pad assignments ..................................18 4.0. functional description ..........................19 4.1. pentium a ii processor mobile module ...............19 4.2. l2 cache.............................................................19 4.3. the 443bx host bridge system controller .......19 4.3.1. memory organization .........................................19 4.3.2. reset strap options ...........................................20 4.3.3. pci interface .......................................................20 4.3.4 agp feature set ................................................20 4.4. power management............................................21 4.4.1 clock control architecture..................................21 4.4.2. normal state .......................................................23 4.4.3. auto halt state....................................................23 4.4.4. stop grant state .................................................23 4.4.5. quick start state.................................................23 4.4.6. halt/grant snoop state ...................................23 4.4.7. sleep state..........................................................23 4.4.8. deep sleep state................................................24 4.5. typical pos/str power ....................................24 4.6. electrical requirement .......................................25 4.6.1. dc requirements ...............................................25 4.6.2 ac requirements................................................26 4.6.2.1. system bus clock (bclk) signal quality specifications and measurement guidelines .....................27 4.7. voltage regulator ...............................................27 4.7.1. voltage regulator efficiency ..............................27 4.7.2. control of the voltage regulator ........................28 4.7.2.1. voltage signal definition and sequencing............................................29 4.7.3. power planes: bulk capacitance requirements30 4.7.4. surge current guidelines ...................................31 4.7.4.1. slew-rate control: circuit description............................................33 4.7.4.2. under-voltage lockout: circuit description (v_uv_lockout)...................34 4.7.4.3. over-voltage lockout: circuit description (v_ov_lockout)...................35 4.7.4.4. over-current protection: circuit description ..........................................................35 4.8. active thermal feedback ...................................35 4.9 thermal sensor configuration register.............36 5.0. mechanical specification ......................37 5.1. module dimensions ............................................37 5.1.1. board area ..........................................................37 5.1.2. mmc-1 pin 1 location ........................................38 5.1.3. printed circuit board thickness .........................38 5.1.4. height restrictions ..............................................39 5.2. thermal transfer plate .......................................40 5.3. module physical support ....................................41 5.3.1 module mounting requirements ........................41 5.3.2. module weight ....................................................41 6.0. thermal specification .............................42 6.1. thermal design power .......................................42 6.2 thermal sensor setpoint ....................................42 7.0. labeling information ...............................43 8.0. environmental standards ....................45
4 intel a pentium a ii processor mobile module mmc-1 figures figure 1. block diagram of the pentium a ii processor mobile module .........................................................6 figure 2. 280-pin connector footprint pad numbers, module secondary side.........................................18 figure 3. pentium a ii processor mobile module clock control states .......................................................22 figure 4. bclk, tck, picclk generic clock waveform at the processor core pin .....................................27 figure 5. power-on sequence timing .................................30 figure 6. instantaneous in-rush current model ..................31 figure 7. instantaneous in-rush current .............................32 figure 8. over-current protection circuit.............................33 figure 9. spice simulation using in-rush protection (example only) .....................................................34 figure 10. pentium a ii processor mmc-1 board dimensions with 280-pin connector orientation ....................37 figure 11. pentium a ii 280-pin connector - pin 1 orientation............................................................38 figure 12. printed circuit board thickness..........................39 figure 13. pentium a ii processor mobile module 3-d keep-out zone .....................................................39 figure 14. pentium a ii processor mobile module thermal transfer plate........................................40 figure 15. pentium a ii processor mobile module thermal transfer plate........................................41 figure 16. standoff holes, board edge clearance, and emi containment ring .................................42 figure 17. pentium a ii processor mobile module product tracking code........................................44 tables table 1. module connector signal summary.........................7 table 2. memory signal descriptions .....................................9 table 3. pci signal descriptions ..........................................10 table 4. processor/piix4e sideband signal descriptions.............................................................11 table 5. power management signal descriptions ...............12 table 6. clock signal descriptions .......................................13 table 7. voltage descriptions ...............................................14 table 8. jtag pins................................................................14 table 9. miscellaneous pins..................................................15 table 10. connector pin assignments .................................16 table 11. connector specifications ......................................19 table 12. configuration straps for the 443bx host bridge system controller...................................................20 table 13. mobile pentium a ii processor clock state characteristics........................................................24 table 14. mobile pentium a ii processor pos/str power..24 table 15. pentium a ii processor mobile module power specifications 1 ......................................................25 table 16. pentium a ii processor mobile module ac specifications (bclk) ............................................26 table 17. bclk signal quality specifications at the processor core ......................................................27 table 18. typical voltage regulator efficiency ....................28 table 19. voltage signal definitions and sequences ..........29 table 20. capacitance requirements per power plane ......30 table 21. thermal sensor smbus address table ...............35 table 22. thermal sensor configuration register ...............36 table 23. pentium a ii processor mobile module (mmc-1) maximum power specifications.............................43 table 24. environmental standards......................................45
5 intel a pentium a ii processor mobile module mmc-1 1.0 introduction this document provides the technical information for integrating the pentium a ii processor mobile module connector 1 (mmc-1) into the latest notebook systems for todays notebook market. building around this modular design gives the system manufacturer these advantages: avoids complexities associated with designing high- speed processor core logic boards. provides an upgrade path from previous pentium a ii processor mobile modules using a standard interface. 1.1 revision history this is the first version of this document. 2.0. architecture overview the pentium a ii processor mobile module is a highly integrated assembly containing the mobile pentium ii processor core, the intel 443bx host bridge system controller, and system level support. the pentium ii processor mobile module has a 66-mhz system bus speed and runs at speeds of 300 mhz, 266 mhz, and 233 mhz. the pentium ii processor mobile module includes a second- level cache of pipeline burst sram supporting up to 512 kb. the zz snooze mode featured in previous mobile modules is no longer supported. instead, the pentium ii processor mobile module supports the stop clock mode for the l2 srams. the clock signals to the l2 srams are stopped or parked in a low power state by the processor. the piix4e pci/isa bridge is one of two large-scale integrated devices of the intel a 440bx pciset. a notebooks system electronics must include a piix4e device to connect to the pentium ii processor mobile module. the piix4e provides extensive power management capabilities and supports the second integrated device, the 443bx host bridge. key features of the intel 443bx host bridge system controller include the dram controller that supports edo at 3.3v with a burst read at 7-2-2-2 (60 ns) or sdram at 3.3v with a burst read at 8-1-1-1 (66 mhz, cl=2). the 443bx host bridge also provides a pci clkrun# signal to request the piix4e to regulate the pci clock on the pci bus. the 82443bx clock enables self-refresh mode of edo or sdram during suspend mode and is compatible with smram (c_smram) and extended smram (e_smram) modes of power management. e_smram mode supports write-back cacheable smram up to 1 mb. a thermal transfer plate (ttp) on the 443bx host bridge and the mobile pentium ii processor provides heat dissipation and a standard thermal attach point for the notebook manufacturers thermal solution. an on-board voltage regulator converts the system dc voltage to the processors core and i/o voltage. isolating the processor voltage requirements allows the system manufacturer to incorporate different processor variants into a single notebook system. supporting input voltages from 5v to 21v, the processor core voltage regulator enables an above 80 percent peak efficiency and decouples processor voltage requirements from the system. the pentium ii processor mobile module also incorporates active thermal feedback (atf) sensing, compliant to the acpi rev 1.0 specification. a system management bus (smbus) supports the internal and external temperature sensing with programmable trip points.
6 intel a pentium a ii processor mobile module mmc-1 figure 1 illustrates the block diagram of the pentium a ii processor mobile module. 280 pin board-to-board connector cpu volt. reg. 5v-21v processor core voltage pci bus memory bus pclk1 hclk1 443bx "northbridge" v_3 hclk0 piix4e sidebands atf sense smbus fsb mobile pentium? ii processor core pb sram v_3s tag v_3s pb sram v_3s 2.5v backside bus i/o voltage r_gtl dclkwr dclkrd bsb figure 1. block diagram of the pentium a ii processor mobile module
7 intel a pentium a ii processor mobile module mmc-1 3.0 module connector interface 3.1 signal definition this section provides information on signal groups for the pentium a ii processor mmc-1. the signals are variably defined for compatibility with future intel mobile modules. table 1 provides a list of signals by category and the corresponding number of signals in each category. for proper signal termination, please contact your intel sales representative. table 1. module connector signal summary signal group number memory 108 pci 56 processor/piix4e sideband 9 power management 8 clocks 8 voltage: v_dc 10 voltage: v_3s 20 voltage: v_5 1 voltage: v_3 5 voltage: v_cpuio 3 jtag 7 miscellaneous & module id 5 ground 32 reserved 8 total 280
8 intel a pentium a ii processor mobile module mmc-1 3.1.1. signal list the following notations are used to denote the signal type: i input pin o output pin o d open drain output pin. this pin requires a pull up resistor. i d open drain input pin. this pin requires a pull up resistor. i/o d input / open drain output pin. this pin requires a pull up resistor. i/o bi-directional input / output pin the signal description also includes the type of buffer used for a particular signal: gtl+ open drain gtl+ interface signal. pci pci bus interface signals. cmos the cmos buffers are low voltage ttl compatible signals. they are also 3.3v outputs with 5.0v tolerant inputs.
9 intel a pentium a ii processor mobile module mmc-1 3.1.2. memory (108 signals) table 2 lists the memory interface signals. table 2. memory signal descriptions name type voltage description mecc[7:0] i/o cmos v_3 memory ecc data: these signals carry memory ecc data during access to dram. these pins are not implemented on the mmc-1 and are reserved for future use. rasa[5:0]# or csa[5:0]# o cmos v_3 row address strobe (edo): these pins select the dram row. chip select (sdram): these pins activate the sdrams. sdram accepts any command when its cs# pin is active low. casa[7:0]# or dqma[7:0] o cmos v_3 column address strobe (edo): these pins select the dram column. input/output data mask (sdram): these pins act as synchronized output enables during a read cycle and as a byte mask during a write cycle. mab[9:0]# mab[10] mab[12:11]# mab[13] o cmos v_3 memory address (edo/sdram): this is the row and column address for dram. the 443bx host bridge system controller has two identical sets of address lines (maa and mab#). the pentium a ii processor mobile module supports only the mab set of address lines. for additional addressing features, please refer to the intel a 440bx pciset datasheet . mwe[a, b]# o cmos v_3 memory write enable (edo/sdram): mwea# should be used as the write enable for the memory data bus. sras[a, b]# o cmos v_3 sdram row address strobe (sdram): when active low, this signal latches row address on the positive edge of the clock. this signal also allows row access and pre-charge. scas[a, b]# o cmos v_3 sdram column address strobe (sdram): when active low, this signal latches column address on the positive edge of the clock. this signal also allows column access. cke[a, b] o cmos v_3 sdram clock enable (sdram): when these signals are deasserted, sdram enters power-down mode. ckeb is nc and not used by the system electronics. md[63:0] i/o cmos v_3 memory data: these signals are connected to the dram data bus. they are not terminated on the pentium a ii processor mobile module. notes: 1. dqma signals are non-inverted. please refer to 82443bx spec update 2. mab[13] is a non-inverted address signal. please refer to 82443bx spec update.
10 intel a pentium a ii processor mobile module mmc-1 3.1.3. pci (56 signals) table 3 lists the pci interface signals. table 3. pci signal descriptions name type voltage description ad[31:0] i/o pci v_3 address/data: the standard pci address and data lines. the address is driven with frame# assertion, and data is driven or received in following clocks. c/be[3:0]# i/o pci v_3 command/byte enable: the command is driven with frame# assertion and byte enables corresponding to supplied or requested data are driven on the following clocks. frame# i/o pci v_3 frame: assertion indicates the address phase of a pci transfer. negation indicates that one more data transfers are desired by the cycle initiator. devsel# i/o pci v_3 device select: the 443bx host bridge drives this signal when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. irdy# i/o pci v_3 initiator ready: asserted when the initiator is ready for data transfer. trdy# i/o pci v_3 target ready: asserted when the target is ready for a data transfer. stop# i/o pci v_3 stop: asserted by the target to request the master to stop the current transaction. plock# i/o pci v_3 lock: indicates an exclusive bus operation and may require multiple transactions to complete. when lock# is asserted, non- exclusive transactions may proceed. the 443bx supports lock for cpu initiated cycles only. pci initiated locked cycles are not supported. req[4:0]# i pci v_3 pci request: pci master requests for pci. gnt[4:0]# o pci v_3 pci grant: permission is given to the master to use pci. phold# i pci v_3 pci hold: this signal comes from the expansion bridge; it is the bridge request for pci. the 443bx host bridge will drain the dram write buffers, drain the processor-to-pci posting buffers, and acquire the host bus before granting the request via phlda#. this ensures that gat timing is met for isa masters. the phold# protocol has been modified to include support for passive release. phlda# o pci v_3 pci hold acknowledge: the 443bx host bridge drives this signal to grant pci to the expansion bridge. the phlda# protocol has been modified to include support for passive release. par i/o pci v_3 parity: a single parity bit is provided over ad[31:0] and c/be[3:0]#. serr# i/o pci v_3 system error: the 443bx asserts this signal to indicate an error condition. please refer to the intel a 440bx pciset datasheet (order number 290633-001) for further information. clkrun# i/o d pci v_3 clock run: an open-drain output and input. the 443bx host bridge requests the central resource (piix4e) to start or maintain the pci clock by asserting clkrun#. the 443bx host bridge tri- states clkrun# upon deassertion of reset (since clk is running upon deassertion of reset).
11 intel a pentium a ii processor mobile module mmc-1 name type voltage description pci_rst# i cmos v_3 reset: when asserted, this signal asynchronously resets the 443bx host bridge. the pci signals also tri-state, compliant with pci rev 2.1 specifications. 3.1.4 processor and piix4e sideband (9 signals) table 4 lists the processor and piix4e sideband interface signals. these voltage levels are determined by v_cpuio. table 4. processor/piix4e sideband signal descriptions name type voltage description ferr# o cmos v_cpuio numeric coprocessor error: this pin functions as a ferr# signal supporting coprocessor errors. this signal is tied to the coprocessor error signal on the processor and is driven by the processor to the piix4e. cpurst n/c cmos v_cpuio processor reset: the signal is not used in the pentium a ii processor mmc-1. ignne# id cmos v_cpuio ignore error: this open drain signal is connected to the ignore error pin on the processor and is driven by the piix4e. init# id cmos v_cpuio initialization: init# is asserted by the piix4e to the processor for system initialization. this signal is an open drain. intr id cmos v_cpuio processor interrupt: intr is driven by the piix4e to signal the processor that an interrupt request is pending and needs to be serviced. this signal is an open drain. nmi id cmos v_cpuio non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor. the piix4e isa bridge generates an nmi when either serr# or iochk# is asserted, depending on how the nmi status and control register is programmed. this signal is an open drain. a20m# id cmos v_cpuio address bit 20 mask: when enabled, this open drain signal causes the processor to emulate the address wraparound at one mb which occurs on the intel 8086 processor. smi# id cmos v_cpuio system management interrupt: smi# is an active low synchronous output from the piix4e that is asserted in response to one of many enabled hardware or software events. the smi# open drain signal can be an asynchronous input to the processor. however, in this chip set smi# is synchronous to pclk. stpclk# id cmos v_cpuio stop clock: stpclk# is an active low synchronous open drain output from the piix4e that is asserted in response to one of many hardware or software events. stpclk# connects directly to the processor and is synchronous to pciclk. when the processor samples stpclk# asserted it responds by entering a low power state (quick start). the processor will only exit this mode when this signal is deasserted.
12 intel a pentium a ii processor mobile module mmc-1 3.1.5 power management (8 signals) table 5 lists the power management interface signals. the sm_clk and sm_data signals refer to the two-wire serial smbus interface. although this interface is currently used solely for the digital thermal sensor, the smbus contains reserved serial addresses for future use. see section 4.9 for more details. table 5. power management signal descriptions name type voltage description oem_pu i cmos v_3 oem pullup: this pullup resistor is not required on the intel a pentium a ii processor mobile module. this signal is used by previous intel mobile module generations. l2_zz n/c cmos v_cpuio low-power mode for cache sram: this signal is not used on the intel a pentium a ii processor mobile module. it is a signal used by previous intel mobile module generations. sus_stat# i cmos v_3always 1 suspend status: this signal connects to the sus_stat1# output of piix4e. it provides information on host clock status and is asserted during all suspend states. vr_on i v_3s vr_on: voltage regulator on. this 3.3v (5v tolerant) signal controls the operation of the voltage regulator. vr_on should be generated as a function of the piix4e susb# signal which is used for controlling the suspend state b voltage planes. this signal should be driven by a digital signal with a rise/fall time of less than or equal to 1 us. (vil (max)=0.4v, vih (min)=3.0v). see figure 5 for proper sequencing of vr_on. vr_pwrgd o v_3s vr_pwrgd: this signal is driven high to indicate that the voltage regulator is stable and is pulled low using a 100k resistor when inactive. it can be used in some combination to generate the system pwrgood signal. sm_clk i/o d cmos v_3 serial clock: this clock signal is used on the smbus interface to the digital thermal sensor. ensure proper termination based upon the system management bus specification, revision 1.0 . sm_data i/o d cmos v_3 serial data: open-drain data signal on the smbus interface to the digital thermal sensor. ensure proper termination based upon the system management bus specification, revision 1.0 . atf_int# o d cmos v_3 atf interrupt: this signal is an open-drain output signal of the digital thermal sensor. note: v_3always: 3.3v supply. it is generated whenever v_dc is available and supplied to piix4e resume well.
13 intel a pentium a ii processor mobile module mmc-1 3.1.6 clock (8 signals) table 6 lists the clock interface signals. table 6. clock signal descriptions name type voltage description oem_pd i cmos v_3 oem pull-down: it is renamed from pci_ref and this pulldown resistor is not required on the intel a pentium a ii processor mobile module. it is a signal used by previous intel mobile module generations. pclk i pci v_3s pci clock in: pclk is an input to the module from the ckdm66-m clock source and is one of the systems pci clocks. this clock is used by all of the 443bx host bridge logic in the pci clock domain. this clock is stopped when the piix4e pci_stp# signal is asserted and/or during all suspend states. hclk[1:0] i cmos v_cpuio host clock in: these clocks are inputs to the module from the ckdm66-m clock source and are used by the processor and the 443bx host bridge system controller. this clock is stopped when the piix4e cpu_stp# signal is asserted and/or during all suspend states. susclk n/c cmos v_3 suspend clock : this signal is not used on the intel a pentium a processor mobile module. fqs[1:0] o cmos v_3s frequency status: this signal provides status of the host clock frequency to the system electronics. these signals are static and are pulled either low or high to the v_3s voltage. fqs1 fqs0 frequency 0 0 60 mhz 0 1 66 mhz 1 0 reserved 1 1 reserved cpu3.3_2.5# o cmos v_cpuio clock voltage select: provides status to the system electronics about the voltage level at which the ckdm66-m clock generator should be operating. this signal is pulled low by the intel a pentium a ii processor mobile module.
14 intel a pentium a ii processor mobile module mmc-1 3.1.7 voltages (39 signals) table 7 lists the voltage signal definitions. table 7. voltage descriptions name type number description v_dc i 10 dc input: 5v - 21v v_3s i 20 susb# controlled 3.3v: power-managed 3.3v supply. an output of the voltage regulator on the system electronics. this rail is off during str, std, and soff. v_5 i 1 susc# controlled 5v: power-managed 5v supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. v_3 i 5 susc# controlled 3.3v: power-managed 3.3v supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. v_cpuio o 3 processor i/o ring: powers processor interface signals such as the piix4e open-drain pullups for the processor/piix4e sideband signals and the ckdm66-m clock source. 3.1.8 jtag (7 signals) table 8 lists the itp/jtag signals, which the system electronics can use to implement a jtag chain and itp port, if desired. the jtag signals provided can not be used as an itp port, since the definition of the itp interface has changed between the pentium a processor and mobile pentium ii processor generations. table 8. jtag pins name type voltage description tdo o v_cpuio jtag test data out: serial output port. tap instructions and data are shifted out of the processor from this port. tdi i v_cpuio jtag test data in: serial input port. tap instructions and data are shifted into the processor from this port. tms i v_cpuio jtag test mode select: controls the tap controller change sequence. tclk i v_cpuio jtag test clock: testability clock for clocking the jtag boundary scan sequence. trst# i v_cpuio jtag test reset: asynchronously resets the tap controller in the processor. itp(1:0) itp1 itp0 o i v_cpuio debug port signals: currently defined for the generation of pentium a processors. these signals are not used in the pentium ii processor mobile module, and should not be connected. note: dbrest# (reset target system) on the itp debug port can be logically anded with vr_pwrgd to piix4es pwrok.
15 intel a pentium a ii processor mobile module mmc-1 3.1.9 miscellaneous (45 signals) table 9 lists the miscellaneous signals. table 9. miscellaneous pins name type number description module id[3:0] o cmos 4 module revision id : these pins track the revision level of the intel a pentium a ii processor module. a 100k pull up resistor to v_3s is required on these signals and to be placed on the system electronics for these signals. ppp_pp# o cmos 1 pentium a ii processor or pentium processor present : a high on this signal indicates to the piix4e isa bridge config1 pin that the processor module used is based on the pentium pro architecture; a low indicates that it is of the pentium processor family. this signal is allowed to float on pentium ii processor mobile modules and requires a 100k pull up resistor to v_3s on the system electronics. this signal is grounded. ground i 32 ground. reserved rsvd 8 unallocated reserved pins and should not be connected.
16 intel a pentium a ii processor mobile module mmc-1 3.2. connector pin assignments table 10 lists the signals for each pin of the connector from the pentium a ii processor mobile module to the notebook manufacturers system electronics. refer to section 3.3 for the pin assignments of the pads on the connector. table 10. connector pin assignments pin# row row row row aa ab ba bb 1 gnd gnd gnd gnd 2 md31 md63 mid0 mid1 3 md30 md61 reserved reserved 4 md29 md62 v dc v dc 5 md27 md58 v dc v dc 6 v3s v3s vdc vdc 7 md28 md60 v dc v dc 8 md26 md56 v dc v dc 9 md25 md57 reserved reserved 10 md24 md59 mid2 mid3 11 gnd gnd gnd gnd 12 cas3#/d q m3 cas7#/d q m7 ad00 frame# 13 cas6#/d q m6 cas2#/d q m2 ad01 lock# 14 ma00 ma01 ad02 devsel# 15 ckea ckeb ad03 irdy# 16 v3s v3s v3s v3s 17 ma02 ma04 ad04 trdy# 18 ma03 ma05 ad05 stop# 19 md55 md22 ad06 phold# 20 md54 md23 ad07 phlda# 21 gnd gnd gnd gnd 22 md51 md20 ad08 pci rst# 23 md52 md21 ad09 par 24 md53 md19 ad10 serr# 25 md49 md17 ad11 re q 0# 26 v3s v3s v3s re q 1# 27 md48 md18 ad12 re q 2# 28 md50 md16 ad13 re q 3# 29 srasa# scasa# ad14 gnt0# 30 srasb# scasb# ad15 gnt1# 31 gnd gnd gnd gnd 32 mwea# mecc3 ad16 gnt2# 33 mweb# mecc7 ad17 gnt3# 34 ras0#/cs0# mecc6 ad18 l2 zz 35 ras1#/cs1# mecc2 ad19 reserved 36 v3s v3s v3s v3s 37 md14 mecc1 ad20 reserved 38 md11 mecc5 ad21 ppp pp# 39 md15 mecc4 ad22 clkrun# 40 gnd gnd gnd gnd 41 md10 mecc0 ras2#/cs2# sm clk 42 md13 md43 ras3#/cs3# sm data 43 md09 md41 ras4#/cs4# atf int# 44 md08 md45 ras5#/cs5# susclk 45 v3s v3s v3 v3
17 intel a pentium a ii processor mobile module mmc-1 pin# row row row row 46 md12 md42 ad23 sus stat# 47 ma06 md40 ad24 v 3 48 ma07 md44 ad25 oem pu 49 ma08 md46 ad26 vr on 50 gnd gnd gnd gnd 51 ma09 md47 ad27 vr pwrgd 52 cas1#/dqm1 cas5#/dqm5 ad28 v 3 53 cas4#/dqm4 cas0#/dqm0 ad29 v 3 54 ma10 ma12 ad30 reserved 55 v 3s v 3s v 3s reserved 56 ma11 ma13 ad31 init# 57 md39 md07 c/be0# v cpuio 58 md37 md02 c/be1# intr 59 md38 md00 c/be2# cpurst 60 gnd gnd gnd gnd 61 md36 md04 c/be3# stpclk# 62 md33 md01 ignne# smi# 63 md35 md03 ferr# nmi 64 md32 md06 a20m# v 5 65 md34 md05 vcpuio vcpuio 66 v 3s v 3s tdo trst# 67 oem pd pclk itp0 tdi 68 fqs0 fqs1 itp1 tms 69 hclk1 hclk0 cpu3.3 2.5# tclk 70 gnd gnd gnd gnd
18 intel a pentium a ii processor mobile module mmc-1 3.3 pin and pad assignments the pentium a ii processor mmc-1 is a surface mount, 0.6- mm pitch, and 280-pin connector. there are currently three different sized mating connector receptacles offered for the pentium ii processor mobile module. see section 5.1.4. height restrictions or contact your local intel sales representative for more information. figure 2 shows the connector pad assignments for the manufacturers system electronics. this footprint is viewed from the secondary side of the pentium ii processor module (the side of the printed circuit board on which the 280-pin connector is soldered). aa 70 aa 1 ab 70 ab 1 ba 70 ba 1 bb 70 bb 1 280-pin connector footprint oem pad assignments (viewed from the secondary side of the processor module) figure 2. 280-pin connector footprint pad numbers, module secondary side
19 intel a pentium a ii processor mobile module mmc-1 table 11 summarizes the key specifications for the mmc-1. table 11. connector specifications parameter condition specification material contact copper alloy housing thermo plastic molded compound: lcp electrical current 0.5 a voltage 50 vac insulation resistance 100 m w min. at 500 vdc termination resistance 20 m w max. at 20 mv open circuit with 10 ma capacitance 5 pf max. per contact mechanical mating cycles 50 cycles connector mating force 0.9n (90 gf) max. per contact contact un-mating force 0.1n (10gf) min. per contact 4.0. functional description 4.1. pentium a ii processor mo bile module the pentium a ii processor mobile module supports the mobile pentium ii processor core with 32 kb l1 data cache, the 443bx host bridge system controller, and system level support. the mobile pentium ii processor includes a 66-mhz system bus speed and offers speeds of 300 mhz, 266 mhz, and 233 mhz. 4.2. l2 cache the mobile pentium a ii processor cores internal cache is enhanced by a second-level cache using a high- performance pipeline burst sram. sram uses a dedicated high-speed bus into the processor core. the l2 cache can support 512 mb of system memory. the maximum amount of cacheable system memory supported by the 443bx host bridge system controller is 256 mb with 16-mbit drams. (the system controller can support up to 1 gb of system memory using 64-mbit technology.) the pentium ii processor mobile module has two 100-pin tqfp footprints for 512k direct-mapped write-back l2 cache. the pentium ii processor mobile module supports the stop clock mode of power management for the l2 srams. in this mode, the clock signals to the synchronous srams are parked in a low power state. 4.3. the 443bx host bridge system controller intels a 443bx host bridge system controller combines the mobile pentium a ii processor bus controller, the dram controller, and the pci bus controller. the 443bx host bridge has multiple power management features designed specifically for notebook systems such as: clkrun#, a feature that enables controlling of the pci clock on or off. the 443bx host bridge suspend modes, including suspend-to-ram (str), suspend-to-disk (std), and powered-on-suspend (pos). system management ram (smram) power management modes, including compatible smram (c_smram) and extended smram (e_smram). c_smram is the traditional smram feature implemented in all intel pci chipsets. e_smram is a new feature that supports write-back cacheable smram space up to 1 mb. to minimize power consumption while the system is idle, the internal 443bx host bridge clock is turned off (gated off). this is accomplished by setting the g_clk enable bit in the power management register in the 443bx through the system bios. pentium ii processor mobile modules support only the 443bx host bridge features in mobile compatible mode. refer to intels latest revision of the 443bx host bridge specification for complete details. 4.3.1. memory organization the memory interface of the 443bx host bridge is available at the mmc-1 allowing support for the following: one set of memory control signals sufficient to support up to three so_dimm sockets and six banks of sdram at 66 mhz. one cke signal for all banks. memory features not supported by the mmc-1 are:
20 intel a pentium a ii processor mobile module mmc-1 support for eight banks of memory. mixed mode memory (edo and sdram). second set of memory address lines (maa[13:0]). error correction code (ecc). 100-mhz sdram (and psb). accelerated graphics port (agp). the 443bx host bridge system controller includes edo and sdram. these memory types should not be mixed in the system, so that all dram in all rows (ras[5:0]#) must be of the same technology. the 443bx host bridge system controller targets 60-ns edo drams and 66-mhz sdrams. the pentium a ii processor mobile modules clocking architecture supports the use of sdram. due to the tight timing requirements of 66-mhz sdram clocks, all host and sdram clocks may be generated from the same clocking architecture on the oems system electronics. for complete details about using sdram memory, and for trace length guidelines, refer to the mobile pentium? ii processor / 82443bx pciset advanced platform recommended design and debug practices. refer to the intel 440bx pciset datasheet for details on memory device support, organization, size, and addressing. 4.3.2. reset strap options several strap options on the memory address bus define the behavior of the pentium a ii processor mobile module after reset. other straps are allowed to override the default settings. table 12 shows the various straps and their implementation. table 12. configuration straps for the 443bx host bridge system controller signal function module default setting mab[12]# host frequency select no strap. (66 mhz default). mab[11]# in order queue depth no strap. (maximum queue depth is set, i.e. 8). mab[10] quick start select strapped high on the module for quick start mode. mab[9]# agp disable strapped to disable agp. mab[7]# mm config strapped for mmc-1 compatible mode. mab[6]# host bus buffer mode select strapped high on the module for mobile fsb buffers. 4.3.3. pci interface the pci interface of the 443bx host bridge is available at the mmc-1. the 443bx host bridge supports the pci clockrun protocol for pci bus power management. in this protocol, pci devices assert the clkrun# open-drain signal when they require the use of the pci interface. refer to the pci mobile design guide for complete details on the pci clockrun protocol. the 443bx host bridge is responsible for arbitrating the pci bus. in mmc-1 mode, the 443bx host bridge can only support up to five pci bus masters. there are five pci request/grant pairs, req[4:0]# and gnt[4:0]#, available on the mmc-1. the 443bx host bridge system controller is compliant with the pci 2.1 specification, which improves the worst case pci bus access latency from earlier pci specifications. as detailed in the pci specification, the 443bx host bridge supports only mechanism #1 for accessing pci configuration space. this implies that signals ad[31:11] are available for pci idsel signals. however, since the 443bx host bridge is always device #0, ad11 will never be asserted during pci configuration cycles as an idsel. the 443bx reserves ad12 for the agpbus, which is not supported by mmc-1. thus, ad13 is the first available address line usable as an idsel. ad18 should be used by the piix4e. 4.3.4 agp feature set the intel a pentium a ii mmc-1 family does not support the agp interface. however, the mmc-2 family supports agp. please refer to the pentium ii processor mobile module: mobile module connector 2 (mmc-2) datasheet.
21 intel a pentium a ii processor mobile module mmc-1 4.4. power management 4.4.1 clock control architecture the pentium a ii processor mobile modules clock control architecture (figure 3) is optimal for notebook designs. the clock control architecture consists of seven different clock states: normal, stop grant, auto halt, quick start, halt/grant snoop, sleep, and deep sleep states. the auto halt state provides a low power clock state that can be controlled through the software execution of the hlt instruction. the quick start state provides a very low power, low exit latency clock state that can be used for hardware controlled idle computer states. the deep sleep state provides an extremely low power state that can be used for power-on suspend computer states, which is an alternative to shutting off the processors power. compared to the pentium processor mobile module exit latency of 1 msec, the exit latency of the deep sleep state has been reduced to 30 m sec in the pentium ii processor mobile module. the stop grant and quick start clock states are mutually exclusive, for example a strapping option on signal a15# chooses which state is entered when the stpclk# signal is asserted. strapping the a15# signal to ground at reset enables the quick start state. otherwise, asserting the stpclk# signal puts the pentium ii processor into the stop grant state. the stop grant state has a higher power level than the quick start state and is designed for smp platforms. the quick start state has a much lower power level, but it can only be used in uniprocessor (up) platforms. performing state transitions not shown in figure 3 is neither recommended nor supported.
22 intel a pentium a ii processor mobile module mmc-1 halt/grant snoop normal state hs=false stop grant auto halt hs=true quick start sleep deep sleep (!stpclk# and !hs) or stop break stpclk# and !qse and sga snoop occurs snoop serviced stpclk# and qse and sga (!stpclk# and !hs) or reset# snoop serviced snoop occurs !stpclk# and hs stpclk# and !qse and sga hlt and halt bus cycle halt break snoop serviced snoop occurs stpclk# and qse and sga !stpclk# and hs !slp# or reset# slp# bclk stopped bclk on and !qse bclk stopped bclk on and qse notes: halt break C a20m#, binit#, flush#, init#, intr, nmi, preq#, reset#, smi# hlt C hlt instruction executed hs C processor halt state qse C quick start state enabled sga C stop grant acknowledge bus cycle issued stop break C binit#, flush#, reset# figure 3. pentium a ii processor mobile module clock control states
23 intel a pentium a ii processor mobile module mmc-1 4.4.2. normal state the normal operating mode for the mobile pentium a ii processor. the processors core clock is running and the processor is actively executing instructions. 4.4.3. auto halt state this is a low-power mode entered through the hlt instruction. the power level is similar to the stop grant state. a transition to the normal state is made by a halt break event (one of the following signals going active: nmi, intr, binit#, init#, reset#, flush#, or smi#). asserting the stpclk# signal while in the auto halt state will cause the processor to transition to the stop grant or quick start state, which issues a stop grant acknowledge bus cycle. deasserting stpclk# will cause the processor to return to the auto halt state without issuing a new halt bus cycle. the smi# (system management interrupt) is recognized in the auto halt state. the return from the smi handler can be to either the normal state or the auto halt state. see the intel ? architecture software developers manual, volume iii: system programmers guide for more information. no halt bus cycle is issued when returning to the auto halt state from system management mode (smm). the flush# signal is serviced in the auto halt state. after flushing the on-chip, the processor will return to the auto halt state without issuing a halt bus cycle. transitions in the a20m# and preq# signals are recognized while in the auto halt state. 4.4.4. stop grant state the stop grant state is not supported in the intel mobile modules the processor enters this mode with the assertion of the stpclk# signal when it is configured for stop grant state (via the a15# strapping option). the processor is still able to respond to snoop requests and latch interrupts. latched interrupts will be serviced when the processor returns to the normal state. only one occurrence of each interrupt event will be latched. a transition back to the normal state can be made by the deassertion of the stpclk# signal or the occurrence of a stop break event (a binit#, flush#, or reset# assertion). the processor will return to the stop grant state after the completion of a binit# bus initialization unless stpclk# has been deasserted. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the stop grant state after initialization until stpclk# is deasserted. if the flush# signal is asserted, the processor will flush the on-chip caches and return to the stop grant state. a transition to the sleep state can be made by the assertion of the slp# signal. while in the stop grant state, assertions of smi#, init#, intr, and nmi (or lint[1:0]) will be latched by the processor. these latched events will not be serviced until the processor returns to the normal state. only one of each event will be recognized upon return to the normal state. 4.4.5. quick start state this is a mode entered with the assertion of the stpclk# signal when it is configured for the quick start state (via the a15# strapping option). in the quick start state the processor is only capable of acting on snoop transactions generated by the system bus priority device. because of its snooping behavior, quick start can only be used in up configuration. a transition to the deep sleep state can be made by stopping the clock input to the processor. a transition back to the normal state (from the quick start state) is made only if the stpclk# signal is deasserted. while in this state the processor is limited in its ability to respond to input. it is incapable of latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to flush# or binit# assertions. while the processor is in the quick start state, it will not respond properly to any input signal other than stpclk#, reset#, or bpri#. if any other input signal changes, then the behavior of the processor will be unpredictable. no serial interrupt messages may begin or be in progress while the processor is in the quick start state. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the quick start state after initialization until stpclk# is deasserted. 4.4.6. halt/grant snoop state the processor will respond to snoop transactions on the system bus while in the auto halt, stop grant, or quick start state. when a snoop transaction is presented on the system bus the processor will enter the halt/grant snoop state. the processor will remain in this state until the snoop has been serviced and the system bus is quiet. after the snoop has been serviced, the processor will return to its previous state. if the halt/grant snoop state is entered from the quick start state, then the input signal restrictions of the quick start state still apply in the halt/grant snoop state, except for those signal transitions that are required to perform the snoop. 4.4.7. sleep state the sleep state is a very low power state in which the processor maintains its context and the phase-locked loop (pll) maintains phase lock. the sleep state can only be entered from the stop grant state. after entering the stop grant state the slp# signal can be asserted, causing the processor to enter the sleep state. the slp# signal is not recognized in the normal or auto halt states. the processor can be reset by the reset# signal while in the sleep state. if reset# is driven active while the processor is in the sleep state then slp# and stpclk# must immediately be driven inactive to ensure that the processor correctly initializes itself. input signals (other than reset#) may not change while the processor is in the sleep state or transitioning into or out of
24 intel a pentium a ii processor mobile module mmc-1 the sleep state. input signal changes at these times will cause unpredictable behavior. thus, the processor is incapable of snooping or latching any events in the sleep state. while in the sleep state the processor can enter its lowest power state, the deep sleep state. removing the processors input clock puts the processor in the deep sleep state. picclk may be removed in the sleep state. the sleep state is not supported in intel mobile modules. 4.4.8. deep sleep state the deep sleep state is the lowest power mode the processor can enter while maintaining its context. the deep stopping the bclk input to the processor enters sleep state, while it is in the sleep state or quick start state. for proper operation, the bclk input should be stopped in the low state. the processor will return to the sleep state or quick start state from the deep sleep state when the bclk input is restarted. due to the pll lock latency, there is a 30-msec delay after the clocks have started before this state transition happens. picclk may be removed in the deep sleep state. picclk should be designed to turn on when bclk turns on when transitioning out of the deep sleep state. the input signal restrictions for the deep sleep state are the same as for the sleep state, except that reset# assertion will result in unpredictable behavior. table 13. mobile pentium a ii processor clock state characteristics clock state exit latency processor power snooping ? system uses normal n/a varies yes normal program execution. auto halt approximately 10 bus clocks 1.2 w yes s/w controlled entry idle mode. stop grant 10 bus clocks 1.2 w yes h/w controlled entry/exit mobile throttling. quick start through snoop, to halt/grant snoop state: immediate through stpclk#, to normal state: 10 bus clocks 0.5 w yes h/w controlled entry/exit mobile throttling. halt/grant snoop a few bus clocks after the end of snoop activity. not specified yes supports snooping in the low power states. sleep to stop grant state 10 bus clocks 0.5 w no h/w controlled entry/exit desktop idle mode support. deep sleep 30 msec 150 mw no h/w controlled entry/exit mobile powered-on suspend support. note: not 100% tested. specified at 50 c by design/characterization. 4.5. typical pos/str power table 14 shows the pos/str power values. table 14. mobile pentium a ii processor pos/str power state typical mmc1 power pos 910 mw str 3 mw note: these are average values of measurement on several typical modules and are guidelines only.
25 intel a pentium a ii processor mobile module mmc-1 4.6. electrical requirement the following section provides information on the dc requirements for the pentium a ii processor mobile module. 4.6.1. dc requirements please refer to table 15 for power supply design criteria to ensure compliance with the dc power requirements. table 15. pentium a ii processor mobile module power specifications 1 voltage plane minimum voltage typical voltage absolute maximum voltage dc minimum operatin g current dc typical operatin g current dc maximum operatin g current instan- taneous peak current leakage 3 typical 25c v_dc 5.0v 12.0v 4 21.0v 75 ma 0.6a 1 2.85a 2 14.2a 4.0 ua v_5 4.75v 5.0v 5.25v 13 ma 32 ma 60 ma 500 ma 1 ua v_3 3.135v 3.3v 3.465v 0.2a 0.7a 1.60a 2.0a 1.1 ma v_3s 3.135v 3.3v 3.465v 30 ma 0.2a 0.52a 0.7a 2 ua v_cpuio 2.375v 2.5v 2.625v 0.0 ma 4 50 ma 4 80 ma 0.0 ma 0.0 ma notes: 1. v_dc is set for 18v in order to determine typical v_dc current. 2. v_dc is set for 5v in order to determine maximum operating v_dc current. 3. leakage current that can be expected when vr_on is deactivated and v_dc is st ill applied. 4. these values are oem system dep endent.
26 intel a pentium a ii processor mobile module mmc-1 4.6.2 ac requirements table 16 provides the bclk ac requirements. table 16. pentium a ii processor mobile module ac specifications (bclk) at the processor core pins 1, 2, 3 t# parameter min nom max unit figure notes system bus frequency 66.67 mhz all processor core frequencies 4 t1: bclk period 15.0 ns 4, 5 t2: bclk period stability 250 ps 6, 7, 8 t3: bclk high time 5.3 ns at >1.8v t4: bclk low time 5.3 ns at <0.7v t5: bclk rise time 0.175 0.875 ns (0.9v-1.6v) 8 t6: bclk fall time 0.175 0.875 ns (1.6vC0.9v) 8 notes: 1. unless otherwise noted, all specifications in this table apply to all intel mobile modules. 2. all ac timings for the gtl+ signals are referenced to the bclk rising edge at 1.25v at the processor core pin. all gtl+ sign al timings (address bus, data bus, etc.) are referenced at 1.00v at the processor core pins. 3. all ac timings for the cmos signals are referenced to the bclk rising edge at 1.25v at the processor core pin. all cmos sign al timings (compatibility signals, etc.) are referenced at 1.25v at the processor core pins. 4. the internal core clock frequency is derived from the system bus clock. the system bus clock to core clock ratio is determined during initialization as described and is predetermined by the pentium ii processor mobile module. 5. the bclk period allows a +0.5 ns tolerance for clock driver variation. see the ck97 clock synthesizer/driver specification for further information. 6. measured on the rising edge of adjacent bclks at 1.25v. the jitter present must be accounted for as a component of bclk skew between devices. 7. the clock drivers closed loop jitter bandwidth must be set low to allow any pll-based device to track the jitter created by th e clock driver. the C20 db attenuation point, as measured into a 10 to 20 pf load, should be less than?500 khz. this specification may be ensured by design characterization and/or measured with a spectrum analyzer. see the ck97 clock synthesizer/driver specification for further details. 8. not 100% tested. specified by design characterization as a clock driver requirement.
27 intel a pentium a ii processor mobile module mmc-1 4.6.2.1. system bus clock (bclk) signal quality specifications and measurement guidelines table 17 describes the signal quality specifications at the processor core for the bclk signal. figure 4 describes the signal quality waveform for the bclk at the processor core pins. table 17. bclk signal quality specifications at the processor core t# parameter min nom max unit figure notes v1: bclk v il 0.7 v 4 2 v2: bclk v ih 1.8 v 4 2 v3: v in absolute voltage range C0.8 3.5 v 4 3 v4: rising edge ringback 1.8 v 4 4 v5: falling edge ringback 0.7 v 4 4 bclk rising/falling slew rate 0.8 4 v/ns notes: 1. unless otherwise noted, all specifications in this table apply to all intel mobile modules. 2. bclk must rise/fall monotonically between v il,bclk and v ih, bclk. 3. the system bus clock overs hoot and undershoot specification for the 66-mhz system bus operation. 4. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bcl k signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. 5. for proper signal termination, refer to the clocking guidelines in the mobile pentium a ii processor / 440bx pciset advanced platform recommend design and debug practices. v2 v1 v3 v3 t3 v5 v4 t6 t4 t5 000806 figure 4. bclk, tck, picclk generic clock waveform at the processor core pin 4.7. voltage regulator the dc voltage regulator (dc/dc converter) provides the appropriate core voltage, the i/o ring voltage, and the sideband signal pullup voltage. the voltage range is 5v C 21v. 4.7.1. voltage regulator efficiency table 18 lists the voltage regulator efficiencies.
28 intel a pentium a ii processor mobile module mmc-1 table 18. typical voltage regulator efficiency icore, a 3 v_dc, v i_dc, a 2 efficiency 1 1 5.0 0.370 82.8% 2 5.0 0.702 88.8% 3 5.0 1.044 89.8% 4 5.0 1.404 89.7% 5 5.0 1.762 88.1% 6 5.0 2.144 86.4% 7 5.0 2.528 85.0% 1 12.0 0.159 79.7% 2 12.0 0.295 87.0% 3 12.0 0.438 87.8% 4 12.0 0.584 87.3% 5 12.0 0.736 86.1% 6 12.0 0.890 84.9% 7 12.0 1.043 83.8% 1 21.0 0.091 79.3% 2 21.0 0.170 86.0% 3 21.0 0.253 87.3% 4 21.0 0.340 85.3% 5 21.0 0.429 84.1% 6 21.0 0.519 82.9% 7 21.0 0.617 80.7% notes: 1. these efficiencies will change with future voltage regulators that accommodate wider ranges of input voltages. 2. with v_dc applied and the voltage regulator off, typical leakage is 0.3 ma with a maximum of 0.7 ma. 3. icore indicates the cpu core current being drawn during test and measurement. 4.7.2. control of the voltage regulator the vr_on pin turns the dc voltage regulator on or off. the vr_on pin should be controlled as a function of the susb#, which controls the systems power planes. vr_on should switch high only when the following conditions are met: v_5(s) => 4.5v and v_dc => 4.75v. caution - turning on vr_on prior to meeting these conditions will severely damage the pentium a ii processor mobile module. the vr_pwrgd signal indicates that the voltage regulator power is operating at a stable voltage level. use vr_pwrgd on the system electronics to control power inputs and to gate pwrok to the piix4e. table 19 lists the voltage signal definitions and sequences. figure 5 shows the signal sequencing and the voltage planes sequencing required for normal operation.
29 intel a pentium a ii processor mobile module mmc-1 4.7.2.1. voltage signal definition and sequencing table 19. voltage signal definitions and sequences signal source definitions and sequences v_dc system electronics dc voltage is driven from the power supply and is required to be between 5v and 21v dc. v_dc powers the pentium a ii processor mobile modules dc-to-dc converter for processor core and i/o voltages. it cannot be hot inserted or removed while v_dc is powered on. v_3 system electronics v_3 is supplied by the system electronics for the 443bx. v_5 system electronics v_5 is supplied by the system electronics for the 443bxs reference voltage and the voltage regulator. v_3s system electronics v_3s is supplied by the system electronics for the l2 cache devices. each must be powered off during system str and std states. vr_on system electronics enables the voltage regulator circuit. when driven active high (3.3v) the voltage regulator circuit is activated. the signal driving vr_on should be a digital signal with a rise/fall time of less than or equal to 1 m s. (vil (max)=0.4v, vih (min)=3.0v). see notes below. v_core (also used as host bus gtl+ termination voltage vtt) pentium a ii processor mobile module only; not on module interface. a result of vr_on being asserted, v_core is an output of the dc-dc regulator on the mobile module and is driven to the core voltage of the processor. it is also used as the host bus gtl+ termination voltage, known as vtt. v_bsb_io pentium a ii processor mobile module v_bsb_io is 1.8v. the system electronics uses this voltage to power the l2 cache-to-processor interface circuitry. vr_pwrgd pentium a ii processor mobile module upon sampling the voltage level of v_core (minus tolerances for ripple), vr_pwrgd is driven active high. if vr_pwrgd is not sampled active within 1 sec. of the assertion of vr_on, then the system electronics should deassert vr_on. after vcore is stabilized, vr_pwrgd will assert to logic high (3.3v). this signal must not be pulled up by the system electronics. vr_pwrgd should be anded with v_3s to generate the piix4e input signal, pwrok. the system electronics should monitor vr_pwrgd to verify it is asserted high prior to the active high assertion of piix4e pwrok. v_cpuio pentium a ii processor mobile module v_cpuio is 2.5v. the system electr onics uses this voltage to power the piix4e-to-processor interface circuitry, as well as the hclk(0:1) drivers for the processor clock. notes : 1. the vr_on signal may only be asserted to a logical high by a digital signal only after v_dc>=4.7v, v_5>=4.5v, and v_3>= 3.0v. 2. the rise time and fall time of vr_on must be less than or equal to 1 m s when it goes through its vil to vih. 3. vr_on has its vil (max) = +0.4v and vih (min) = + 3.0v. 4. vr_on needs to rise monotonically through its vil to vih points. 5. vr_on needs to provide an instantaneous in-rush current to the module with the following values: an instantaneous max. of 41 ma with a typical of 0.2 ma; a dc operating max. of 0.1 m a with a typical of 0.0. 6. in going from a valid on to valid off and then back on, vr_on must be low for 1 ms. in addition, the original voltage level requirements for turn-on always need to be met before assertion of vr_on (i.e. v_dc>=4.7v, v5>=4.5v, v_3>=3.0v).
30 intel a pentium a ii processor mobile module mmc-1 power sequence timing v_dc 1. pwrok on i/o board should be active on when vr_pwrgd is active and v_3s is good. 2. cpu_rst from i/o board should be active for a minimum of 6 ms after pwrok is active and pll_stp# and cpu_stp# are inactive. note that pll_stp# is an and condition of rsmrst# and susb# on the piix4e/m. 3. v_dc >= 4.7v, v_5>=4.5v, v_3s>=3.0v. 4. v_cpupu and v_clk are generated on the intel mobile module. 5. this is the 5v power supplied to the processor module connector. this should be the first 5v plane to power up. 6. vr_pwrgd is specifiedto its associated high/active by the module regulator within less than or equal to 6 ms max. after the assertion of vr_on. v_3 v_5 vr_pwrgd v_3s vr_on 0 ms min 0 ms min 0 ms min see note 6 see note 3 v_cpuio/ v_clk see note 5 figure 5. power-on sequence timing in the power-on process, intel recommends that the higher voltage power (v_dc) plane is raised first, followed by the lower power planes (v_5 and v_3), and finally the assertion of vr_on. in the power-off process, the reverse applies so that first vr_on is deasserted, followed by the lower power planes, and finally the higher power plane. 4.7.3. power planes: bulk capacitance requirements in order to provide adequate filtering and in-rush current protection for any system design, bulk capacitance is required. a small amount of bulk capacitance is supplied on the pentium a ii processor mobile module. however, in order to achieve proper filtering additional capacitance should be placed on the system electronics. table 20 details the bulk capacitance requirements for the system electronics when using the pentium ii processor mobile module. table 20. capacitance requirements per power plane power plane capacitance requirements esr ripple current rating v_dc 100 uf, 0.1 uf, 0.01 uf 1 20 m w 1-3.5a 3 20% tolerance at 35v v_5 100 uf, 0.1 uf, 0.01 uf 1 100 m w 1a 20% tolerance at 10v v_3 470 uf, 0.1 uf, 0.01 uf 1 100 m w 1a 20% tolerance at 6v v_3s 100 uf, 0.1 uf, 0.01 uf 1 100 m w n/a 20% tolerance at 6v v_cpuio 2.2 uf, 8200 pf 1 n/a n/a 20% tolerance at 6v notes: 1. placement of above capacitance requirements should be located near the mmc-1. 2. v_cpuio filtering should be located next to the system clock synthesizer. 3. ripple current specification depends on v_dc input. for 5.0v v_dc, a 3.5a device is required. for v_dc at 18v or higher, 1a is sufficient.
31 intel a pentium a ii processor mobile module mmc-1 4.7.4. surge current guidelines this section provides the results of a worst case, surge current analysis. the analysis determines the maximum amount of surge current that the pentium a ii processor mobile module can manage. in the analysis, the pentium ii processor mobile module has two 4.7 m f with an esr of 0.15 w s each. the mmc-1 is approximately 30 m w of series resistance, for a total series resistance of .18 w . if the user powers the system with the a/c adapter (18v), the amount of surge current on the module would be approximately 100a. this information was also used to develop i/o bulk capacitance requirements (see table 20). note : depending on the system electronics design, different impedances may yield different results. the oem should perform a thorough analysis to understand the implications of surge current on their system. figure 6 shows an electrical model used when analyzing instantaneous power-on conditions and figure 7 illustrates the results with a spice simulation. figure 6. instantaneous in-rush current model
32 intel a pentium a ii processor mobile module mmc-1 figure 7. instantaneous in-rush current due to the stringent component height requirements of the pentium a ii processor mobile module, polymerized organic semi-conductor capacitors must be used as input bulk capacitance in the voltage regulator circuit. because of the capacitors susceptibility to high in-rush current, special care must be taken. one way to soften the in-rush current and provide over-voltage and over-current protection is to ramp up v_dc slowly using a circuit similar to the one shown in figure 8.
33 intel a pentium a ii processor mobile module mmc-1 figure 8. over-current protection circuit 4.7.4.1. slew-rate control: circuit description in figure 8, pwr is the voltage generated by applying the ac adaptor or battery. m1 is a low rds (on) p-channel mosfet such as a siliconix* si4435dy. when the voltage on pwr is applied and increased to over 4.75v, the under_voltage_lockout circuit allows r4 to pull up the gate of m3 to start a turn-on sequence. m3 pulls its drain toward ground, forcing current to flow through r2. m1 will not start to source any current until after t_delay with t_delay defined as: t_delay . . r2 c9 ln 1 vt vpwr vgs_max vgs_max . r16 r16 r2 vpwr the manufacturers vgs_max specification of 20v must never be exceeded. however, vgs_max must be high enough to keep the rds (on) of the device as low as possible. after the initial t_delay, m1 will begin to source current and v_dc will start to ramp up. the ramp up time, t_ramp, is defined as: t_ramp . . r2 c9 ln 1 vsat vgs_max t_delay maximum current during the voltage ramping is: i . ctotal vpwr t_ramp
34 intel a pentium a ii processor mobile module mmc-1 with the circuit shown in figure 8, t_delay = 5.53 ms, t_tran = 14.0 ms and i_max = 146 ma. figure 9 shows a spice simulation of the circuit in figure 8. to increase the reliability of tantalum capacitors, use a slew rate control circuit as described in figure 8 and voltage-derate the capacitor about 50 percent. that is, for a maximum input voltage of 18v, use a 35v, low esr capacitor with high ripple current capability. place five, 22 f/35v capacitors on the baseboard directly at the v_dc pins of the pentium a ii processor mmc-1. the slew rate control circuit should also be applied to every input power source to the system v_dc to provide the most protection. if all power is ored together at the pwr node, there is still a potential problem. for example, if a 3x3 li-ion battery pack is powering the system (12v at pwr), and the ac adaptor (18v) is plugged into the system, current will immediately be sourced to the pwr node and v_dc. this is because the slew rate control is already on. therefore, the slew rate control must be applied to every input power source to provide the most protection. . figure 9. spice simulation using in-rush protection (example only) 4.7.4.2. under-voltage lockout: circuit description (v_uv_lockout) the circuit shown in figure 8 provides an under-voltage protection and locks out the applied voltage to the pentium a ii processor mobile module to prevent an accidental turn-on at low voltage. the output of this circuit, pin 1 of the lm339 comparator, is an open-collector output. it is low when the applied voltage at pwr is less than 4.75v. this voltage can be calculated with the following equation with the voltage across d7 as 2.5v. (d7 is a 2.5-v reference generator). v_uv_lockout . vref 1 r17 . r18 r25 r18 r25 = v_uv_lockout 4.757 volt
35 intel a pentium a ii processor mobile module mmc-1 4.7.4.3. over-voltage lockout: circuit description (v_ov_lockout) the pentium a ii processor mobile module is specified to operate with a maximum input voltage of 21v. this circuit locks out the input voltage if it exceeds the maximum 21v. the output of this circuit, pin 14 of the lm339 comparator, is an open-collector output. it is low when the applied voltage at pwr is more than 21v. this voltage can be calculated with the following equation: v_ov_lockout . . vref r26 r26 r27 1 r24 r23 = v_ov_lockout 20.998 volt 4.7.4.4. over-current protection: circuit description figure 8 shows the circuit detecting an over-current condition and cuts off the input. two different current limit trip points cause the different maximum current drain at different input voltages. assuming the ac adaptor is 18v and the battery is a 3x3 li-ion configuration with a minimum voltage of 7.5v, the maximum current for the above circuit can be calculated using the following expression: with ac adaptor (i_wadaptor): i_wadaptor . vref vbe_q1 r14 r13 r1 i_wadaptor = 0.989 amp without ac adaptor (i_woadaptor): i_woadaptor . vref vbe_q1 . r14 r33 r14 r33 r13 r1 i_woadaptor = 2.375 amp 4.8. active thermal feedback table 21 identifies the addresses allocated for the smbus thermal sensor. table 21. thermal sensor smbus address table function fixed address ad bits (6:4) selectable address ad bits (3:0) thermal sensor 100 1110 reserved 010 1010 reserved 010 1011 note : the thermal sensor used is compliant with smbus addressing. please refer to the pentium? ii processor thermal sensor interface specification .
36 intel a pentium a ii processor mobile module mmc-1 4.9 thermal sensor configuration register the configuration register of the thermal sensor controls the operating mode (auto-convert vs. standby). since the processor temperature varies dynamically during normal operation, auto-convert mode should be used exclusively to monitor processor temperature if the run/stop bit is low, then the thermal sensor enters auto-conversion mode. if the run/stop bit is set high, then the thermal sensor immediately stops converting and enters standby mode. the thermal sensor will still perform temperature conversions in standby mode when it receives a one-shot command. however, the result of a one-shot command during auto-convert mode is not guaranteed. intel recommends that only auto-convert mode should be used. refer to mobile pentium ? ii processor and pentium ? ii processor mobile module thermal sensor interface specifications , rev.1.0. table 22 shows the format of the configuration register. table 22. thermal sensor configuration register bit name reset state function 7 msb mask 0 masks smbalert# when high. 6 run/sto p 0 standby mode control bit. if low, the device enters auto- convert mode. if high, the device immediately stops converting, and enters standby mode where the one-shot command can be performed. 5 C 0 rfu 0 reserved for future use. note: all rfu bits should be written as 0 and read as dont care for programming purposes.
37 intel a pentium a ii processor mobile module mmc-1 5.0. mechanical specification 5.1. module dimensions this section provides the physical dimensions for the pentium a ii processor mmc-1. 5.1.1. board area figure 10 shows the board dimensions and the orientation for the pentium a ii processor mmc-1.these dimensions are necessary to accommodate the next generation of intel mobile modules and pci 443bx chipset controllers. figure 10. pentium a ii processor mmc-1 board dimensions with 280-pin connector orientation
38 intel a pentium a ii processor mobile module mmc-1 5.1.2. mmc-1 pin 1 location figure 11 shows the location of pin 1 of the 280-pin mmc-1 as referenced to the adjacent mounting hole. secondary side dimensions are in inches figure 11. pentium a ii processor mobile module board dimensions with 280-pin connector - pin 1 orientation 5.1.3. printed circuit board thickness figure 12 shows the pentium a ii processor mobile module profile and the associated minimum and maximum thickness of the printed circuit board (pcb). the range of pcb thickness allows for different pcb technologies to be used with current and future intel mobile modules. note: the system manufacturer must ensure that the mechanical restraining method or system-level emi contacts are able to support this range of pcb thickness, to ensure compatibility with future intel mobile modules.
39 intel a pentium a ii processor mobile module mmc-1 min: 0.90 mm max: 1.10 mm processor module printed circuit board figure 12. printed circuit board thickness 5.1.4. height restrictions figure 13 shows the mechanical stackup and associated component clearance requirements. this is referred to as the module keep-out zone and should not be entered or altered. one of three possible mating connectors (4 mm, 6mm, and 8mm) establish board-to-board clearance between the pentium a ii processor mobile module and the system electronics. information on these connectors can be obtained from your local intel representative. figure 13. pentium a ii processor mobile module 3-d mechanical drawing
40 intel a pentium a ii processor mobile module mmc-1 5.2. thermal transfer plate a thermal transfer plate (ttp) on the mobile pentium a ii processor and the 443bx provides for heat dissipation. the ttp may vary on different generations of intel mobile modules. the ttp provides the thermal attach point, where a system manufacturer can use a heat pipe, a heat spreader plate, or a thermal solution to transfer heat through the notebook system. attachment dimensions for the oem thermal interface block to the ttp are provided in the following figures 14 and 15. the system manufacturer should use the exact dimensions for maximum contact area to the ttp. this also protects against warpage of the ttp. if warpage occurs, the thermal resistance of the pentium ii processor mobile module could be adversely affected. a thermal elastimer or thermal grease should be used to reduce the thermal resistance. the ttp thermal resistance between the processor core to the system interface (top of the ttp) is less than 1c per watt. the oem thermal interface block should be secured with 2.0 mm screws using a maximum torque of 1.5 C 2.0 kg*cm (equivalent to 0.147 - .197 n*m). the thread length of the 2.00-mm screws should be 2.25-mm gageable thread (2.25-mm minimum to 2.80- mm maximum). the following figures 14 and 15 detail the mechanical dimensions of the ttp and the thermal attach point. figure 14. pentium a ii processor mobile module thermal transfer plate
41 intel a pentium a ii processor mobile module mmc-1 figure 15. pentium a ii processor mobile module thermal transfer plate 5.3. module physical support figure 16 shows the standoff support hole patterns, the board edge clearance, the dimensions of the emi containment ring, and the keep-out area. these hole locations and board edge clearances will remain fixed for all intel mobile modules. 5.3.1 module mounting requirements three mounting holes secure the module to the electronics. see figure 11 for mounting hole locations. intel recommends that all three mounting holes be used to ensure long term reliability of the system. the hole patterns also have a plated surrounding ring, which can be uses with a metal standoff for emi shielding purposes. the board edge clearance includes a 0.762 mm (0.030 in) width emi containment ring around the perimeter of the module. this ring is on each layer of the module pcb and is grounded. the metal on the surface of the module is exposed for emi shielding purposes. standoffs should be used to provide support for the installed pentium ii processor mobile module. the distance from the bottom of the module pcb to the top of the oem system electronics board with the connectors mated is 4.0 mm +0.16 mm / -0.13 mm. however warpage of the baseboard may vary and should be calculated into the final. all calculations can be made with the intel mmc-1 standoff/receptacle height spreadsheet . information on this spreadsheet can be obtained from your local intel representative. 5.3.2. module weight the weight of the pentium a ii processor mobile module is 48g +/- 2g.
42 intel a pentium a ii processor mobile module mmc-1 hole detail, 3 places standoff holes and board edge keepouts (top side) 0.762 mm width of emi containment ring 1.27+/- 0.19 mm board edge to emi ring 2.54+/-0.19 mm keepout area 3.81+/-0.19 mm board edge to hole centerline 3.81+/-0.19 mm 4.45 mm diameter grounded ring + 0.050 mm - 0.025 mm hole diameter 2.413 mm figure 16. standoff holes, board edge clearance, and emi containment ring 6.0. thermal specification 6.1. thermal design power the maximum thermal design power (tdp) is the maximum total power dissipation under normal operating conditions at nominal vcc while executing the worst case power instruction mix. this includes the power dissipated by all of the relevant components of the pentium a ii processor mobile module. system thermal designs do not need the capability to dissipate this level of power if they incorporate some type of thermal feedback fail-safe system. the use of nominal vcc in this measurement accounts for the thermal time constant of the package/system. the power supply must be centered at nominal vcc such that during transients the vcc levels stay within the vcc vcc_delta (%) range. the duration of surges to vcc + vcc_delta (%) are less than the thermal time constant. during all operating environments, the processor case temperature, t proc , must be within the specified range of 0 c to 100 c. see table 23 for the maximum tdp specification. 6.2 thermal sensor setpoint the thermal sensor in the pentium a ii processor mobile module implements the smbalert# signal described in the smbus specification. smbalert# is always asserted when the temperature of the processor core thermal diode or the thermal sensor internal temperature exceeds either the upper or lower temperature thresholds. smbalert# may also be asserted if the measured temperature equals either the upper or the lower threshold.
43 intel a pentium a ii processor mobile module mmc-1 table 23. pentium a ii processor mobile module (mmc-1) maximum power specifications symbol parameter typ max 1 unit notes tdp 2 mmc-1 thermal design at 300 mhz power ( mmc-1 module) at 266 mhz at 233 mhz 13.9 w module (core, 443bx, voltage regulator, & l2 cache) notes: 1. tdp max is a specification of the total power dissipation of the worst case processor, worst case 443bx, and worst case voltage regulator while executing a worst case instruction mix under normal operating conditions at nominal voltages. not 100% tested. specified by design/characterization. 7.0. labeling information the pentium a ii processor mobile module is tracked in two ways. the first is by the product tracking code (ptc). intel uses the ptc label to determine the assembly level of the module. the ptc label is located on the secondary side of the module as shown in figure 17 and provides the following information. the product tracking code will consist of 13 characters as identified in the above example and can be broken down as follows: example: pmd30005001aa definition: aa - processor module = pm b - pentium a ii processor mobile module = d ccc - speed identity = 300, 266, 233 dd - cache size = 05 (512.) eee - notifiable design revision (start at 001) ff - notifiable processor revision (start at aa) note: for other intel mobile modules, the second field (b) is defined as: pentium a ii processor mobile module (mmc-2) = e
44 intel a pentium a ii processor mobile module mmc-1 figure 17. pentium ii processor mobile module product tracking code the second tracking method is by oem generated software utility. four strapping resistors located on the pentium a ii processor mobile module determine its production level. if connected and terminated properly, up to 16-module revision levels can be determined. an oem generated software utility can then read these id bits with cpu ids and stepping ids to provide a complete module manufacturing revision level. for current ptc and module id bit information, please refer to the latest pentium ii processor mobile module product change notification letter which can be obtained from your local intel sales representative .
45 intel a pentium a ii processor mobile module mmc-1 8.0. environmental standards the environmental standards for the pentium a ii processor mobile module are defined in table 24. table 24. environmental standards parameter condition specification temperature non-operating -40 c to 85 c operating 0 c to 55 c humidity unbiased 85% relative humidity at 55 c voltage v_5 5v +/- 5% v_3 3.3v +/- 5% shock non-operating half sine, 2g, 11 msec unpackaged trapezoidal, 50g, 11 msec packaged inclined impact at 5.7 ft./s packaged half sine, 2 msec at 36 in. simulated free fall vibration unpackaged 5 hz to 500 hz 2.2 grms random packaged 10 hz to 500 hz 1.0 grms packaged 11,800 impacts 2 hz to 5 hz (low frequency) esd human body model 0 to 2 kv (no detectable err)
united states, intel corporation 2200 mission college blvd., p.o. box 58119, santa clara, ca 95052-8119 tel: +1 408 765-8080 japan, intel japan k.k. 5-6 tokodai, tsukuba-shi, ibaraki-ken 300-26 tel: + 81-29847-8522 france, intel corporation s.a.r.l. 1, quai de grenelle, 75015 paris tel: +33 1-45717171 united kingdom, intel corporation (u.k.) ltd. pipers way, swindon, wiltshire, england sn3 1rj tel: +44 1-793-641440 germany, intel gmbh dornacher strasse 1 85622 feldkirchen/ muenchen tel: +49 89/99143-0 hong kong, intel semiconductor ltd. 32/f two pacific place, 88 queensway, central tel: +852 2844-4555 canada, intel semiconductor of canada, ltd. 190 attwell drive, suite 500 rexdale, ontario m9w 6h8 tel: +416 675-2438 printed in usa/96/pod/pmg

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